The invention relates to a device of the vertical MOS-FET type having a planar multicell structure, which is provided in a semiconductor crystal and comprises an assembly of identical elementary cells in the form of a simple polygon, a shortcircuit region being located at the center of each of these cells and each cell having a first island diffused into a layer of a first conductivity type constituting the drain zone of the device, which island is highly doped with impurities of a second conductivity type opposite to the first conductivity type and defines inter alia at the surface of the layer the perimeter of the said drain zone and the form of the cell, and a second island which is locally diffused into the first island. The second island is highly doped with impurities of the first conductivity type, constitutes the source zone, and defines a channel zone located at the surface and mutually separating the second island and the layer of the first conductivity type, and also defines the central short circuit region.
It is known that according to the common solution used nowadays in the manufacture of MOS-FET power devices a planar so-called multicell structure is utilized which consists of a given number of elementary cells connected parallel in a semiconductor crystal and arranged adjacent each other and having a simple geometric form. For example, structures are already known comprising hexagonal cells, so-called "HEXFET" structures, and more recently so-called "SIPMOS" structures comprising square cells or "TRIMOS" structures comprising triangular cells.
These structures comprise a drain zone, a source zone and a channel zone and can be characterized on the one hand by a filling factor corresponding to the ratio: ##EQU1## and on the other hand by the value of their resistance R.sub.ON in the forward direction in the conductive state. With a given configuration, in structures operated at comparatively low voltages, the resistance R.sub.ON is mainly produced by the transverse resistance of the channel, whose value is inversely proportional to the perimeter of the channel, which is the reason why it is important to improve the filling factor P/S.
When considering this filling factor, it has been found that in all cases optimum dimensions exist as to the source zone located within each elementary cell, the ratio P/S being a maximum, which maximum is constant and is theoretically equal to 1/d (where d represents the distance .mu.m between two adjacent source zones, which distance is determined in practice by admissible etching tolerances in the manufacture of the cells).
The examination of the filling factor in the various configurations has also shown that with an equal P/S the cell density is smaller in a structure constituted by triangular cells. In this structure, like in the other structures, the filling factor remains smaller than the value which is theoretically attainable. This is especially due to the fact that the etching tolerances required for the provision in and on the semiconductor crystal of the various elements of each cell lead either to the enlargement of the surface area of the elementary cells with respect to the source zone or to a reduction of the source zone with respect to the source zone of the elementary cell. In both cases, this means in fact that the distance d between the two source zones is increased and the channel perimeter is decreased.
This decrease of the value of the filling factor with respect to the theoretical value thereof is also due to the fact that in the contemporary structures, a shortcircuit region is formed in each elementary cell for defining the potential of the inversion zone, which shortcircuit region generally has a form which is equal to that of the elementary cell.